It is well known in the art to isolate regions of silicon from one another on a silicon substrate for the purpose of making active devices in the isolated regions. Early attempts at completely isolating these regions involve lateral isolation techniques by forming a trench around an island of semiconductor material to be isolated and filling the trench with an insulating material such as oxide. An example of this technique can be found in commonly owned U.S. Pat. No. 4,661,832 (Lechaton, et al.).
More recent techniques for isolating regions of semiconductor material have been accomplished by completely isolating the regions not only laterally from adjacent areas but also vertically from the substrate from which it is supported. Examples of this isolation technique can be found in U.S. Pat. No. 4,888,300 (Burton) and "A New SOI Fabrication Technique for Ultrathin Active Layer of Less the 80 nm" by H. Horie, K. Oikawa, H. Ishiwari, T. Yamazaki and S. Ando; Fujitsu Laboratories, Ltd.; 1990 Symposium on VLSI Technology IEEE (Horie, et al.).
Burton teaches a method of isolating active semiconductor regions by utilizing the different etch responsiveness of a buried region in order to form a submerged wall insulating layer between a substrate and an active area. After a standard buried layer has been formed in the substrate through conventional techniques, (e.g., epitaxial processing), a trench is cut into the epitaxial layer to provide access to the buried layer. Then, while suspending in place the portion of the epitaxial layer surrounded by the trench, (by means of an oxide bridge), the underlying region of the buried layer is etched away to form a cavity under the active area. This cavity, as well as the surrounding trench, is filled with a suitable insulating material to thereby isolate the active island from the substrate. An example of a suitable insulating material taught by Burton is polysilicon.
A similar isolation technique is disclosed by Horie, et al.
Although the "floating island" technique taught by Burton and Horie, et al. for isolating semiconductor regions is superior to earlier isolation methods, it is not without problems which render it ineffective. In particular, polysilicon trench structures having an oxide trench sidewall as taught by Burton and Horie, et al. produce a tremendous amount of thermal stress at the interface of the trench or cavity wall and the semiconductor substrate. This stress is manifested in silicon areas by stress induced dislocations which begin at vertical silicon/trench or cavity interfaces and extend into adjacent isolated silicon regions. The structural integrity of the silicon region due to these dislocations is consequently compromised, rendering devices built thereon unreliable.
In addition to the above mentioned problem caused by stress induced dislocations, the floating silicon region is subject to separation problems caused by the formation of oxide wedges resultant from subsequent oxidation steps performed to build devices into or onto the floating silicon region. This occurs because the only exposed areas along the interface between the isolated silicon region and the support structure underneath is at the junction where the vertical walls of the region meet the supporting structure. These oxide wedges compress the isolated silicon region upwards or vertically, and consequently cause additional stress dislocations.
For the above reasons it has been found that the techniques of Burton and Horie, et al. are unacceptable for manufacturing processes. An isolation system which overcomes these deficiencies is therefore highly desirable.